1. Field of the Invention
The present invention relates generally to bus systems for transferring information, such as data and control actions, between multiple processors. More particularly, the present invention relates to a high performance computer bus system for interconnecting plural processors in situations where size constraints of the overall system are an issue.
2. Background Information
Bus systems for interconnecting plural processors are known. For example, it is known to interconnect an array of processors to perform real time image processing, wherein a live video stream is processed in real time to identify specific features within the continuously changing image. A parallel processing array has been used for pipelining the data stream, wherein the processors are interconnected using any of a variety of bus systems, including, bus systems available on VME form factor cards. A fundamental operating principal of conventional bus systems, however, is to permit a very large number of processors to be connected with the bus.
However, conventional array bus systems, like those found in the VME world, tend to be more complex and difficult to implement in small specialized embedded systems. These complexities include interconnection schemes, compatibility issues, data routing, and control methods. Interconnection schemes such as crossbar interconnect require additional wiring needed to support multiple parallel paths. Compatibility and performance issues drive the need for more electronics such as those required to provide additional interfaces for the VME bus and other conventional interfaces found in VME subsystems. Data routing methods used are more prone to momentarily lock out path segments that may prevent some of the processors from receiving messages in the required time. Control methods utilize the VME bus for interfacing to the array which adds overhead. While these types of systems may work well in larger applications they have too much overhead and are therefore not practical for specialized embedded array processor systems. Embedded Systems must maximize performance in a small space (i.e., MIPS per unit Volume) as well as to minimize power consumption. Real time response is also critical in embedded arrays and control functions must be tightly integrated into their design.
In addition, the use of a VME Form Factor is unsuitable where space constraints are a significant factor. For example, when image processing is to be performed on board a manned or unmanned vehicle, efficient use of space becomes a significant constraint. Accordingly, it would be desirable to provide a bus system which can be implemented in a space efficient manner, and which can operate efficiently to optimize data and control action throughput.